Selective voltage binning (SVB) is a technique that was developed in order to reduce power consumption at the “fast” end of the process distribution, while increasing operating speed at the “slow” end of the process distribution. Typically, in SVB, a full process distribution for an IC chip design at a target voltage and a target temperature for the technology at issue and with respect to a target threshold voltage (VT)-type transistor is defined prior to manufacturing (e.g., based on a best case/worst case analysis) or after manufacturing (e.g., based on actual performance measurements taken from performance monitors, such as performance screen ring oscillators (PSROs), associated with the target VT-type transistor on IC chips that are manufactured according to the IC design). It should be understood that a given IC chip design will often incorporate multiple different VT-type transistors (e.g., regular threshold voltage (RVT) transistors, high threshold voltage (HVT) transistors, mezzanine threshold voltage (MVT) transistors, super-high threshold voltage (SHVT) transistors, low threshold voltage (LVT) transistors, ultra-high threshold voltage (UHVT) transistors, etc.) and the target VT-type will be one of these different VT-types (e.g., MVT). Additionally, it should be understood that the performance monitors described above can be on-chip performance monitors and/or in-Kerf performance monitors (i.e., performance monitors located in the Kerf-lines between IC chips manufactured on a semiconductor wafer).
In any case, once defined, the full process distribution is then divided into successive intervals (also referred to as process windows) and different voltage ranges are assigned to each successive interval (i.e., to each process window) such that relatively low supply voltage ranges (minimum supply voltage to maximum supply voltage) within the allowable voltage range for the technology are assigned to intervals at the “fast” end of the process distribution and relatively high voltage ranges are assigned to intervals at the “slow” end of the process distribution. Subsequently, performance measurements are taken from on-chip and/or in-Kerf performance monitors of manufactured IC chips, as discussed above and, based on these performance measurements, the IC chips are sorted into different groups (also referred to as voltage bins) that correspond to different process windows. This process of assigning the IC chips to the different groups that correspond to different process windows based on their specific performance measurements is referred to as selective voltage binning. When such IC chips are shipped for incorporation into products, the voltage ranges associated with their respective voltage bins are noted. Operation of relatively fast IC chips at lower voltage ranges minimizes worst-case power consumption and operation of relatively slow IC chips at higher voltage ranges improves their performance (e.g., increases their operating speed/reduces their delay). Recently, it has been noted that some IC chips with performance measurements that warrant them being placed in a group associated with a process window at the “fast” end of the process distribution actually fail to meet performance requirements when operated at the low minimum supply voltage assigned to that process window.